Conferences

[1] A. Morari, R. Gioiosa, R. W. Wisniewski, B. S. Rosenburg  , T. A. Inglett, and M. Valero. Evaluating the impact of tlb misses on future hpc systems. In 26th IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2012. [ bib ]
[2] G. Kestor, R. Gioiosa, T. Harris, A. Cristal, O. Unsal, M. Valero, and I. Hur. STM2: A parallel stm for high performance simultaneous multi-threading systems. In The 20th IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT), October 2011. [ bib ]
[3] A. Morari, R. Gioiosa, R. W. Wisniewski, F. J. Cazorla, and M. Valero. A quantitative analysis of os noise. In 25th IEEE International Parallel and Distributed Processing Symposium (IPDPS), May 2011. [ bib ]
[4] R. Gioiosa. Towards sustainable exascale computing. In The 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC), September 2010. [ bib ]
[5] V. Jimenez, R. Gioiosa, E. Kursun, F. Cazorla, C. Cher, A. Buyuktosunoglu, P. Bose, and M. Valero. Trends and techniques for energy efficient architectures. In The 18th IEEE/IFIP VLSI System on Chip Conference (VLSI-SoC),, September 2010. [ bib ]
[6] R. Gioiosa, S. A. McKee, and M. Valero. Designing os for hpc applications: Scheduling. In The 2010 IEEE International Conference on Cluster Computing (CLUSTER), September 2010. [ bib ]
[7] V. Jimenez, C. Boneti, F. Cazorla, R. Gioiosa, E. Kursun, C. Cher, C. Isci, A. Buyuktosunoglu, P. Bose, and M. Valero. Power and thermal characterization of power6 system. In The 19th International Conference on Parallel Architectures and Compilation Techniques (PACT), September 2010. [ bib ]
[8] B. Goel, S. A. McKee, R. Gioiosa, K. Singh, M. Bhadauria, and M. Cesati. Portable, scalable, per-core power estimation for intelligent resource management. In The 1st Green Computing Conference, 2010 International (IGCC), August 2010. [ bib ]
[9] C. Luque, M. Moreto, F.J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero. Itca: Inter-thread conflict-aware cpu accounting for cmps. In The International Symposium on Parallel Architectures and Compilation Techniques (PACT09), September 2009. [ bib ]
[10] E. Betti, M. Cesati, R. Gioiosa, and F. Piermaria. Global Operating System for HPC Clusters. The 2009 IEEE International Conference on Cluster Computing (Cluster 2009), August 2009. [ bib ]
[11] P. Radojkovic, V. Cakarevic, F. Cazorla, R. Gioiosa, A. Pajuelo, and J. Verdu. Measuring Operating System Overhead on CMT Processors. In The 20th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD08), Campo Grande, Mato Grosso do Soul, Brazil, October 2008. [ bib ]
[12] C. Boneti, F. Cazorla, R. Gioiosa, C-Y. Cher, A. Buyuktosunoglu, and M. Valero. Software-Controlled Priority Characterization of POWER5 Processor. In The 35th International Symposium on Computer Architecture (ISCA)., Beijing, China, June 2008. [ bib ]
[13] C. Boneti, F. Cazorla, R. Gioiosa, and Mateo Valero. Scheduling real-time systems with explicit resource allocation processors. In the 21st International Conference on Architecture of Computing Systems (ARCS08), Dresden, Germany, February 2008. [ bib ]
[14] C. Boneti, R. Gioiosa, F. J. Cazorla, and M. Valero. A dynamic scheduler for balancing HPC applications. In SC '08: Proc. of the 2008 ACM/IEEE conference on Supercomputing, 2008. [ bib ]
[15] C. Boneti, R. Gioiosa, F. Cazorla, J. Corbalan, J. Labarta, and Mateo Valero. Balancing HPC applications through smart allocation of resources in MT processors. In to appear in the 22nd IEEE Int. Parallel and Distributed Processing Symp. (IPDPS08), Miami, FL, 2008. [ bib ]
[16] R. Gioiosa, J.C. Sancho, S. Jiang, F. Petrini, and K. Devis. Transparent Incremental Checkpoint at Kernel level: A Foundation for Fault Tolerance for Parallel Computers. SC|05 (Supercomputing): Int. Conf. for High Performance Computing, Networking, and Storage, November 2005. http://bravo.ce.uniroma2.it/home/gioiosa/pub/sc05.pdf. [ bib ]
[17] R. Gioiosa, F. Petrini, K. Davis, and F. Lebaillif-Delamare. Analysis of System Overhead on Parallel Computers. In The 4th IEEE Int. Symp. on Signal Processing and Information Technology (ISSPIT 2004), Rome, Italy, December 2004. http://bravo.ce.uniroma2.it/home/gioiosa/pub/isspit04.pdf. [ bib ]

Journals

[1] C. Luque, M. Moreto, F. J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero. CPU accounting for multicore processors. IEEE Transaction on Computers, February 2012. [ bib ]
[2] A. Morari, C. Boneti, F. Cazorla, R. Gioiosa, C. Cher, A. Buyuktosunoglu, P. Bose, and M. Valero. SMT malleability in IBM POWER5 and POWER6 processors. IEEE Transaction on Computers, To appear 2012. [ bib ]
[3] V. Jimenez, F. Cazorla, R. Gioiosa, M. Valero, C. Boneti, E. Kursun, C. Cher, C. Isci, A. Buyuktosunoglu, and P. Bose. Characterizing power and temperature behavior of POWER6-based system. (invited paper). IEEE Journal of Emerging and Selected Topics in Circuits and Systems, September 2011. [ bib ]
[4] V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, C. A. Buyuktosunoglu, P. Bose, and M. Valero. A case for energy-aware accounting and billing in large-scale computing facilities cost metrics and design implications. IEEE Micro, May/June 2011. [ bib ]
[5] C. Luque, M. Moreto, F.J. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero. CPU accounting in CMP processors. Computer Architecture Letters, 2009. [ bib ]
[6] E. Betti, D.P. Bovet, M. Cesati, and R. Gioiosa. Hard real-time performances in multiprocessor embedded systems using ASMP-Linux. Operating System Support for Embedded Real-Time Applications special issue on Eurasip Journal on Embedded Systems, October 2007. [ bib ]

Workshops

[1] G. Kestor, R. Gioiosa, O. Unsal, A. Cristal, and M. Valero. Hardware/software techniques for assisted execution runtime systems. In The 2nd Workshop on Runtime Environments, Systems, Layering and Virtualized Environments (RESoLVE), March 2012. [ bib ]
[2] V. Jimenez, F. Cazorla, R. Gioiosa, E. Kursun, C. Isci, A. Buyuktosunoglu, and M. Valero. A case for energy aware accounting in large scale computing facilities: Cost metrics and implications for processor design. In Workshop on Architectural Concerns in Large Datacenters (ACLD), in conjunction with ISCA, June 2010. [ bib ]
[3] K. Kedzierski, F. Cazorla, R. Gioiosa, A. Buyuktosunoglu, and M. Valero. Power and performance aware reconfigurable cache for cmps. In Workshop on Next Generation Multicore/Manycore Technologies (IFMT), in conjunction with ISCA, June 2010. [ bib ]
[4] M. Paolieri, I. Bonesana, R. Gioiosa, and M. Valero. J-dse: Joint software and hardware design space exploration for application specific processors. In Third Workshop on Programmability Issues for Multi-Core Computers (MULTIPROG), January 2010. [ bib ]
[5] V. Cakarevic, P. Radojkovic, R. Gioiosa, F. Cazorla, J. Verdu, A. Pajuelo, and M. Valero. Understanding the overhead of the spin-lock loop in CMT architectures . In "Workshop on the Interaction between Operating Systems and Computer Architecture" (WIOSCA), in conjunction with ISCA'08, Beijing, China, June 2008. [ bib ]
[6] V. Cakarevic, P. Radojkovic, R. Gioiosa, F. Cazorla, J. Verdu, A. Pajuelo, and M. Valero. Overhead of the spin-lock loop in UltraSPARC T2. the 5th HiPEAC Industrial Workshop, June 2008. [ bib ]
[7] José Carlos Sancho, Fabrizio Petrini, Kei Davis, Roberto Gioiosa, and Song Jiang. Current Practice and a Direction Forward in Checkpoint/Restart Implementations for Fault Tolerance. In First Workshop on System Management Tools for Large-Scale Parallel Systems, Denver, CO, April 2005. Available from http://www.c3.lanl.gov/~fabrizio/papers/survey-checkpoint.pdf. [ bib ]

Technical Reports

[1] E. Betti, D.P. Bovet, M. Cesati, and R. Gioiosa. complete data set for the article "Hard real-time performances in multiprocessor embedded systems using ASMP-Linux". Technical Report SPRGTR002, September 2007. [ bib ]
[2] R. Gioiosa, D.P. Bovet, and M. Cesati. vxWorks driver for Asine ASPMC660 flash card. Technical Report SPRGTV-Q001, July 2006. [ bib ]
[3] M. Cesati, R. Gioiosa, and D.P. Bovet. On the Execution Time of a FFT procedure with and without caches. Technical Report SPRGTV-Q002, July 2006. [ bib ]
[4] R. Gioiosa, D.P. Bovet, and M. Cesati. Real-time tests on vxWorks. Technical Report SPRGTV-Q004, July 2006. [ bib ]

Posters

[1] G. Kestor, R. Gioiosa, A. Cristal, O. Unsal, and M. Valero. Enhancing the performance of assisted execution runtime systems. The 17th Architectural Support for Programming Languages and Operating Systems (ASPLOS 2012), March 2012. [ bib ]
[2] A. Morari, F. Piermaria, E., R. Gioiosa, and M. Cesati. Analyzing os noise for hpc systems. The 6th HiPEAC ACACES 2010., July 2010. [ bib ]

Others

[1] R. Gioiosa. High Performance Computing Clusters. Ph.D. Thesis, May 2006. [ bib ]
 
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